As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

The Wavelogic family of products is widely used in Ciena's optical fiber transmission solutions and is one of the main contributors to Ciena's success in the telecommunications industry. To further strengthen our team, we are looking for a hardworking digital verification engineer who will be involved in the verification of these products, working within a team of digital design engineers, verification engineers and architects. Your role as a digital verification engineer will be required to thoroughly simulate and validate functional blocks and subsystems for the Wavelogic family of products.

How you will make an impact:

• As a digital verification engineer you are required to read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects
• You will be held responsible for the complete and detailed validation of one or more architectural functional blocks by using an appropriate combination of simulation, formal and coverage methods
• You will contribute to verification planning, functional coverage definition and possibly formal verification test plans
• You will be accountable for the creation or integration of the test bench components, agents, scoreboard, and test scenarios related to your architectural functional block using System Verilog UVM and/or C where applicable.
• You will perform coverage-driven verification, monitor regressions and debug resulting failures with the help of the function's designer.
• Reporting on status updates on a regular basis

The Must Haves:

• Expert-level experience (3 years +) in digital design verification of complex circuits
• Electrical or computer engineering, computer science or other applicable scientific degree at MEng/MSc level
• Expertise in SV-UVM, SVA and C++ coding
• Expertise in creating comprehensive verification plans from specifications
• Expertise in building verification environments using SV-UVM and C++
• Familiar with metric-driven verification methods including functional coverage
• Familiar with EDA verification tools and flows from major vendors
• A highly motivated self-starter, able to work independently, while being a great teammate
• Ability to methodically solve complex technical problems
• Excellent organization, written and oral (English) interpersonal skills.
• Basic communication skills in German.

Assets:

• Experience with formal verification methods
• Experience with coherent DSP architectures
• Experience with standards and protocols such as OTN/FlexO/B100G, Ethernet (100GE+)
• Experience with using GIT for source code management and revision tracking
• Experience with using Jira for schedule planning, assignment tracking and bug reporting
• Familiarity with programming languages such as Python, Make, bash, object-oriented programming, C, C++

The above lists are intended to describe the general nature and level of work, and they are not intended to be a comprehensive list of all responsibilities, duties and skills required to be qualified and to be performed by the selected candidate. You will have an opportunity to better understand the role through the interview experience.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.